SemiconFab NAND 3D
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3D NAND CTF 128-Tier Macaroni Cell
STEP 01/10 基底与源极

P-Well 基底与底层共用源极板(Source Plate)成形

P-Well Substrate & Bottom Common Source Plate Formation

在单晶硅基底上注入形成 P-Well 阱区，随后沉积并热退火形成重掺杂 N+ 多晶硅与硅化钨（WSi/W）复合下源极导电层（Source Plate），为全阵列垂直存储串提供统一的源极电位（Vss）。

制造机台 (Tool)
高能大束流离子注入机 + 立式扩散退火炉
Applied Materials Varian / TEL TELINDY
材料与结构 (Material)
P-Type Si 单晶硅 + N+ Poly-Si / WSi 复合层
源极导电层厚度: ~120nm | 杂质浓度: 1e20 cm⁻³
工艺核心目的与机理

构建 3D NAND 垂直存储串阵列的坚固物理与电气底座。在先进 CuA (CMOS under Array) 架构中，外围逻辑控制电路更置于此层下方，实现极高硅片利用率。

3D NAND Charge Trap Flash (CTF) Fabrication Process: 10-Step Industrial Engineering Breakdown

This interactive digital twin details the complete industrial fabrication sequence of modern 3D NAND vertical memory strings, featuring alternating oxide-nitride (ONON) multi-layer stacks, high aspect ratio (>60:1) channel punch holes, hollow Macaroni poly-silicon channels, and replacement gate tungsten metallization.

10-Step 3D NAND Semiconductor Fabrication Sequence

  1. Step 1: P-Well Substrate & Bottom Common Source Plate Formation

    Forming P-well on 300mm single-crystal silicon wafer, followed by depositing and annealing heavy N+ poly-Si and tungsten silicide (WSi/W) composite lower source plate providing global Vss ground across the array.

    Equipment: High-Energy Ion Implanter (AMAT Varian) + Vertical Diffusion Anneal Furnace (TEL TELINDY). Materials: P-Type Si Substrate, N+ Poly-Si / WSi Source Plate (Thickness: ~120nm).

  2. Step 2: Alternating Oxide-Nitride (ONON) Multi-Layer Dielectric Stack Deposition

    PECVD continuously deposits dozens to hundreds of alternating nanoscale bilayers of SiO2 (inter-tier isolation, ~25nm) and sacrificial Si3N4 (sacrificial gate tier, ~30nm) with mechanical stress compensation.

    Equipment: Plasma Enhanced Chemical Vapor Deposition (PECVD) System (Lam Research Vector / AMAT Producer GT). Materials: Alternating SiO2 & Si3N4 Bilayers (Stack Height: >5.5μm).

  3. Step 3: Extreme High Aspect Ratio (>60:1) Channel Hole Cryogenic Plasma Etch

    Using thick amorphous carbon hardmask (ACL) and cryogenic fluorocarbon plasma RIE to punch vertical cylindrical channel holes straight through all ONON layers down to the source plate with exceptional verticality.

    Equipment: Cryogenic Extreme HAR Dielectric RIE Etcher (Tokyo Electron TEL Tactras / Lam Vantex). Materials: Vertical Memory Channel Voids (Aspect Ratio: >60:1, Top CD: ~75nm, Bottom CD: ~55nm).

  4. Step 4: ALD Charge Trap Memory Film Stack (Blocking / Si3N4 Trap / Tunnel Oxide)

    Atomic Layer Deposition conforms along deep hole sidewalls, sequentially coating High-k blocking oxide (Al2O3/SiO2), charge trap storage film (high-density Si3N4), and bandgap-engineered tunnel oxide (SiO2/SiON).

    Equipment: Ultra-Conformal Vertical Furnace ALD (TEL TELINDY Plus / ASM Pulsar). Materials: Al2O3 (~5nm) + Si3N4 Trap (~6nm) + SiO2 Tunnel (~3nm).

  5. Step 5: Poly-Si Vertical Conduction Channel & Core Oxide ('Macaroni') Fill

    Conformal LPCVD deposition of a thin (~10nm) poly-silicon channel tube, filling the remaining hollow core with insulating SiO2 macaroni rod, and plugging the top with N+ poly drain contact.

    Equipment: Low-Pressure CVD (LPCVD) + Oxide CMP System (AMAT Producer / Ebara F-REX). Materials: Thin Poly-Si Conduction Shell + Macaroni SiO2 Core + N+ Drain Poly Plug.

  6. Step 6: Slit Trench (Wordline Cut) Anisotropic Deep Dry Etch

    Anisotropic plasma dry etching cuts deep vertical slit trenches between channel columns through all ONON layers down to the source plate, completely exposing the lateral edges of alternating tiers.

    Equipment: Slit Deep RIE Etcher (Lam Research Kiyo / AMAT Centura). Materials: Deep Slit Trenches (Width: ~75nm, Aspect Ratio: >70:1).

  7. Step 7: Hot Phosphoric Acid Selective Nitride Strip (Lateral Gate Cavity Release)

    Injecting hot phosphoric acid (H3PO4, ~160°C) via slit trenches selectively dissolves all sacrificial Si3N4 layers (selectivity > 100:1 over SiO2) to release hollow lateral gate cavities.

    Equipment: Automated High-Temperature Wet Etch Station (TEL CELLESTA / SCREEN SU-3200). Materials: Hot Phosphoric Acid (H3PO4) wet chemistry, releasing hollow horizontal gate shelves.

  8. Step 8: Conformal ALD/CVD Tungsten (W) Wordline Gate Replacement Metallization

    ALD TiN barrier deposition and deep CVD Tungsten metallization filling all horizontal cavities through the slit, followed by recess etch-back to separate monolithic wordlines.

    Equipment: Ultra-Conformal ALD/CVD Metallization System (Lam Research ALTUS / AMAT Olympia). Materials: TiN Liner (~2nm) + Metallic Tungsten (W) Horizontal Wordline Plates.

  9. Step 9: Slit Sidewall Isolation Spacer & Common Source Line (CSL) Metallization

    Depositing SiO2 dielectric sidewall spacers inside the slit trench, opening the floor, and filling with tungsten to form the solid vertical Common Source Line (CSL) wall.

    Equipment: PECVD Spacer + Tungsten CVD + CMP System (Applied Materials Reflexion LK). Materials: SiO2 Dielectric Spacers + Solid Tungsten (W) Vertical CSL Wall.

  10. Step 10: Drain Contact Vias & Orthogonal Bitline (BL) Top Metallization

    Depositing interlayer dielectric (ILD), etching vias to each macaroni channel drain plug, and fabricating orthogonal copper/tungsten bitlines crossing perpendicular to wordlines.

    Equipment: Dual-Damascene Etcher + Electroplating Copper (ECD) System (Lam Research SABRE / AMAT Endura). Materials: Tungsten Vias + Orthogonal Copper/Tungsten Bitlines.

Frequently Asked Questions (FAQ) on 3D NAND Flash Fabrication

Why did 3D NAND transition from Floating Gate to Charge Trap Flash (CTF)?
Floating Gate stores electrons in conductive polysilicon islands, where a single oxide defect leaks the entire charge. Charge Trap Flash (CTF) stores electrons in physically isolated, non-conductive quantum defect traps within a silicon nitride (Si3N4) layer. Local defects do not cause global charge leakage, enabling thinner dielectrics, lower voltages, and eliminating cell-to-cell capacitive crosstalk.
What is the Macaroni channel structure in 3D NAND?
Instead of filling the deep channel hole with solid polysilicon, a thin (~10nm) annular polysilicon channel tube is deposited along the inner wall, while the center is filled with insulating silicon dioxide ('macaroni' core). This eliminates bulk defects and grain boundaries of thick polysilicon, reducing string resistance and boosting read drive current.
How does the Replacement Gate process work in 3D NAND?
Rather than etching refractory metals through hundreds of layers, the initial stack is grown as alternating SiO2 and sacrificial Si3N4. After memory holes are completed, deep slit trenches are cut and hot phosphoric acid dissolves the sacrificial Si3N4. Metallic tungsten (W) is then deposited through the slit into the vacant lateral cavities, forming low-resistance monolithic control gates.